Port Declaration
Dynamic Variables
Behavioral
Data Flow
Conditions
Bitwise Operators
Operators
Values
Numbers
Comparator
Mux
Register
Counter
ETC_ControlPath_block
ETC_DataPath_block
ETC_TestBench_block
Event_DataPath_block
Event_ControlPath_block
Event_TestBench_block
Finite State Machine
RAM Block
Clock Divider
Instance_block
I2C_Protocol
ALU_BLOCK
SISO_BLOCK
PIPO_BLOCK
D_FLIP-FLOP
jk_ff
half_adder
and_tl
dram
_4_bit_unsigned_up_counter_with_asynchronous_clear
full_adder

Verilog Code